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Hardware Submodules
3
Hardware Submodules
This section describes the major sections of the M5253 demo board.
3.1
Processor
The MCF5253 processor is the fundamental control chip on the M5253 demo board. This is a
version 2 (V2) ColdFire processor running at a maximum core speed of 140 MHz. MCF5253 implements
an 8 KB instruction cache, three UART channels, two timers, 128 KB of SRAM, a QSPI (queued serial
peripheral interface) module, two I 2 C modules, three I 2 S modules, an IDE module, a dedicated ATA
interface with DMA support, two FlexCAN modules, an OTG USB 2.0 controller with integrated physical
interface, real-time clock (RTC), a flash memory stick interface, 60 parallel I/O ports (which are
multiplexed with other signals), and the system integration module (SIM). All of the core-processor
registers are 32 bits wide except for the status register (SR) which is 16 bits wide. This processor
communicates with the external devices over a 16 bits wide data bus, D[31:16]. The processor has a logic
to generate up to four chip selects, and support for a bank of SDRAMs. This board has brought out almost
every silicon feature for evaluation and developing the customer design.
3.2
Resets
The system reset signal is coming from the power management IC MC34702 with a reset button. The reset
signal feeds the CPU, flash, BDM, and DM9000 devices. This signal also appears on the connector J17 for
external use.
3.3
System Clock
This board uses a 11.2896 MHz crystal for the system main clock input CRIN.
The system PLL output-clock equation is as follows:
Eqn. 1
PSTCLK =
Fin ? ×
2 ? × VCXODIV
PLLDIV × ? CPUDIV × * VCXOOUT
Following table is the clock configuration:
Table 2. System Clock Configuration
Fin (MHz)
11.2896
11.2896
11.2896
11.2896
CPUDIV
2
2
3
4
CRSEL
0
0
0
0
VCXODIV
62
42
51
51
PLLDIV
5
4
4
4
VCXOOUT
1
1
1
1
PSTCLK (MHz)
140 (default)
120
96
72
Here is the example code to configure the system running at 140 MHz:
M5253 Demo Board User Manual, Rev. 0
4
Freescale Semiconductor
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